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1 features synchronous switching regulator controller (v core ) dual n-channel mosfet synchronous buck design v 2 tm control topology 200ns transient loop response 5-bit dac with 1% tolerance hiccup mode overcurrent protection 65ns adaptive fet non-overlap time nonsynchronous switching regulator controller (v i/o ) single n-channel mosfet buck design adjustable output with 2% tolerance system power management pentium ii system v core and v i/o controlled by a single ic power-good output monitors v core switching regulator output ovp signal monitors v core switching regulator output package option cs5132h dual output cpu buck controller cs5132h description application diagram 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 v id2 v id3 v id4 c off1 comp1 v out1 v fb1 v ffb1 v id1 v id0 pwrgd ovp v cc1 gatel pgnd gateh lgnd v cc2 9 17 18 v ffb2 gate 19 20 v fb2 c off2 v out2 comp2 21 22 23 24 24l so wide 5v/12v to 2v/16a for pentium ii v cc(core) , 5v/12v to 3.3v/8a for v i/o pentium is a registered trademark of intel corporation. v 2 is a trademark of switch power, inc. december, 2001 - rev. 2 on semiconductor 2000 south county trail, east greenwich, ri 02818 tel: (401)885?600 fax: (401)885?786 n. american technical support: 800-282-9855 web site: www.cherry?emi.com archive device not recommended for new design the cs5132h is a dual output cpu power supply controller. it con- tains a synchronous dual nfet buck controller utilizing the v 2 tm control method to achieve the fastest possible transient response and best overall regulation. the cs5132h also contains a second nonsynchronous nfet buck con- troller. these synchronous and nonsynchronous buck regulators are designed to power the core and i/o logic of the latest high perfor- mance cpus. the cs5132h incor- porates many additional features required to ensure the proper operation and protection of the cpu and power system. the cs5132h dual output provides the industry? most highly integrated solution, minimizing external com- ponent count, total solution size, and cost. the cs5132h is specifically designed to power intel? pentium ii processor and includes the following features: 5-bit dac and fixed 1.23v refer- ence, power-good output, hiccup mode overcurrent protection, adaptive voltage positioning, and overvoltage protection. the cs5132h will operate over an 8.4v to 20v range and is available in 24 lead surface mount package. +5v +12v +5v +3.3v (v i/o ) v cc(core) v id0 v id1 v id3 v id2 v id4 gate q3 pcb trace (freecurrent sensing element) 6.6m ? l2 3.5 h mbrd835l v out2 10v 510 ? v ffb2 2k 1% 1.18k 1% v fb2 c off2 v cc1 v cc2 lgnd gate(h) q1 1.2 h l1 q2 gate(l) comp2 pcb trace (free current sensing element) 3.3m ? 10v 10v 510 ? v ffb1 v out1 pwrgd ovp comp1 c off1 pgnd 23 24 1 2 3 12 11 14 20 16 4 5 21 22 6 8 13 19 17 15 c1 c6-c11 c12 c14 c15 c16 c17 c18-c21 c23-c30 r1 r2 r3 r4 v fb1 7 c3-c5 x 4 510 ? r5 510 ? r6 fs70vsj-03 0.1 f 0.1 f 1200 f 1200 f x 6 1200 f x 8 680pf 0.1 f d1 390pf 1 f 1200 f x 3 9 18 fs70vsj-03 fs70vsj-03 10 10v 10k 100pf 51 ? c13 0.1 f 100 ? 0.01 f 10k r10 c25 r9 r8 r7 c22 +12v c2 1 f
2 cs5132h package pin description package pin # pin symbol function absolute maximum ratings pin symbol pin name v max v min i source i sink v cc1 ic logic and low side driver power input 16v -0.3v n/a 1.5a peak 200ma dc v cc2 ic high side drivers power input 20v -0.3v n/a 3a peak 400ma dc comp1, comp2 compensation pins for the v core 6v -0.3v 1ma 5ma and v i/o error amplifiers. v fb1 , v out1 , v id0-4 , v core voltage feedback input pin, v out2 , v fb2 , v ffb1 , v core output voltage sense pin, v ffb2 voltage id dac input pins, v i/o output voltage 6v -0.3v 1ma 1ma sense pin, v i/o voltage feedback input pin, v core pwm comparator fast feedback pin, v i/o pwm comparator fast feedback pin. c off1 , c off2 off-time pins for the v core and v i/o regulators 6v -0.3v 1ma 50ma gate(h), gate high-side fet drivers for the v core 20v -0.3v 1.5a peak 1.5a peak and v i/o regulators. 200ma dc 200ma dc gate(l) low-side fet driver 16v -0.3v 1.5a peak 1.5a peak 200ma dc 200ma dc pwrgd power-good output 6v -0.3v 1ma 30ma ovp overvoltage protection 15v -0.3v 30ma 1ma pgnd power ground 0v 0v 3a peak n/a 400ma dc lgnd logic ground 0v 0v 40ma n/a 23,24,1,2,3 v ido ?v id4 voltage id dac inputs. these pins are internally pulled up to 5.65v if left open. v id4 selects the dac range. when v id4 is high (logic one), the error amp reference range is 2.125v to 3.525v with 100mv incre- ments. when v id4 is low (logic zero), the error amp reference voltage is 1.325v to 2.075v with 50mv increments. 20 v cc1 input power supply pin for the internal circuitry, and low side gate driver. decouple with filter capacitor to pgnd. 17 gate(h) high side switch fet driver pin for v core section. 18 pgnd power ground for v core and v i/o section. 19 gate(l) low side synchronous fet driver pin. 16 v cc2 input power supply pin for on-board high side gate drivers. decouple with filter capacitor to pgnd. 15 gate high side switch fet driver pin for v i/o section. 21 ovp overvoltage protection pin. goes high when overvoltage condition is detected on v fb1 . 22 pwrgd power-good output. open collector output drives low when v fb1 is out of regulation. operating junction temperature, t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 150? lead temperature soldering: reflow (smd styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 sec max. above 18 3?, 230? peak storage temperature range, t s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150? esd susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv
3 cs5132h block diagram uvlo pgnd + - dac v ffb2 - + 0.25v gate(l) c off2 v fb2 lgnd comp2 ovp pwrgd v fb1 v ffb1 c off1 v cc1 v cc2 - + v out2 q r s fault latch2 vid1 vid2 vid3 vid4 vid0 + - s fault latch1 + - - + + - - + + - off time2 one shot + - 1.06v comp1 gate(h) gate - + + - - + v out1 + - 86mv v cc1 + - - + 86mv current limit1 ea1 pwm comp1 pwm comp2 1.23v ea2 0.25v current limit2 pgnd pgnd pgnd non-overlap logic - + 1.10v off time1 one shot q r discharge comparator discharge comparator package pin # pin symbol function package pin description: continued 14 c off2 off-time capacitor pin. a capacitor from this pin to lgnd sets the off time for the non-synchronous regulator (v i/o ). 13 comp2 v i/o section error amp output. pwm comparator inverting input. a capacitor to lgnd provides error amp compensation. 12 v out2 v i/o section current limit comparator inverting input. 11 v fb2 v i/o section error amp inverting feedback input. 10 v ffb2 v i/o pwm comparator fast feedback non-inverting input. v i/o sec- tion current limit comparator non-inverting input. 9 lgnd logic ground. 7v fb1 v core section error amp inverting input, pwrgd and ovp compara- tor input. 6v out1 v core section current limit comparator inverting input. 5 comp1 v core section error amp output. v core section pwm comparator inverting input. a capacitor to lgnd provides error amp compensa- tion. 4c off1 off-time capacitor pin. a capacitor from this pin to lgnd sets the off time for the synchronous regulator ( v core ). 8v ffb1 v core section pwm comparator fast feedback non-inverting input. v core section current limit comparator non-inverting input.
4 cs5132h electrical characteristics: 0? < t a < 70?; 0? < t j < 125?; v out2 3.5v, 9v v cc1 14v, 9v v cc2 20v; 2.0v dac code (v id4 = v id3 = v id2 = v id1 = 0, v id0 = 1), c gate(h) = c gate(l) = c gate = 3.3nf, c off = 390pf; unless otherwise stated. parameter test conditions min typ max unit v core switching regulator error amplifier v fb1 bias current v fb1 = 0v -1.0 0.1 1.0 a comp1 source current comp1 = 1.2v to 3.6v; v fb1 = 1.9 v 15 30 60 a comp1 sink current comp1=1.2v; v fb1 =2.1v; 30 60 120 a open loop gain c comp1 = 0.1f 80 db unity gain bandwidth c comp1 = 0.1f 20 khz psrr @ 1khz c comp1 = 0.1f 70 db voltage identification dac accuracy (all codes) measure v fb1 = comp1, 25? t j 125?, v cc1 = v cc2 = 12v -1.0 1.0 % v id4 v id3 v id2 v id1 v id0 1 0 0 0 0 3.489 3.525 3.560 v 1 0 0 0 1 3.390 3.425 3.459 v 1 0 0 1 0 3.291 3.325 3.358 v 1 0 0 1 1 3.192 3.225 3.257 v 1 0 1 0 0 3.093 3.125 3.156 v 1 0 1 0 1 2.994 3.025 3.055 v 1 0 1 1 0 2.895 2.925 2.954 v 1 0 1 1 1 2.796 2.825 2.853 v 1 1 0 0 0 2.697 2.725 2.752 v 1 1 0 0 1 2.598 2.625 2.651 v 1 1 0 1 0 2.499 2.525 2.550 v 1 1 0 1 1 2.400 2.425 2.449 v 1 1 1 0 0 2.301 2.325 2.348 v 1 1 1 0 1 2.202 2.225 2.247 v 1 1 1 1 0 2.103 2.125 2.146 v 0 0 0 0 0 2.054 2.075 2.096 v 0 0 0 0 1 2.004 2.025 2.045 v 0 0 0 1 0 1.955 1.975 1.995 v 0 0 0 1 1 1.905 1.925 1.944 v 0 0 1 0 0 1.856 1.875 1.894 v 0 0 1 0 1 1.806 1.825 1.843 v 0 0 1 1 0 1.757 1.775 1.793 v 0 0 1 1 1 1.707 1.725 1.742 v 0 1 0 0 0 1.658 1.675 1.692 v 0 1 0 0 1 1.608 1.625 1.641 v 0 1 0 1 0 1.559 1.575 1.591 v 0 1 0 1 1 1.509 1.525 1.540 v 0 1 1 0 0 1.460 1.475 1.490 v 0 1 1 0 1 1.410 1.425 1.439 v 0 1 1 1 0 1.361 1.375 1.389 v 0 1 1 1 1 1.311 1.325 1.338 v 1 1 1 1 1 1.225 1.250 1.275 v line regulation 9v v cc1 14v 0.01 %/v input threshold v id4 , v id3 , v id2 , v id1 , v id0 1.00 1.25 2.40 v
5 cs5132h parameter test conditions min typ max unit electrical characteristics: 0? < t a < 70?; 0? < t j < 125?; v out2 3.5v, 9v v cc1 14v, 9v v cc2 20v; 2.0v dac code (v id4 = v id3 = v id2 = v id1 = 0, v id0 = 1), c gate(h) = c gate(l) = c gate = 3.3nf, c off = 390pf; unless otherwise stated. input pull-up resistance v id4 , v id3 , v id2 , v id1 , v id0 25 50 100 k ? pull-up voltage 5.48 5.65 5.82 v gate(h) and gate(l) high voltage at 100ma measure v cc1/2 ?ate(l)/(h) 1.2 2.1 v low voltage at 100ma measure gate(l)/(h) 1.0 1.5 v rise time 1.6v < gate(h)/(l) < (v cc1/2 ?2.5v) 40 80 ns fall time (v cc1/2 ?2.5v) > gate(l)/(h) > 1.6v 40 80 ns gate(h) to gate(l) delay gate(h)<2v, gate(l)>2v 30 65 100 ns gate(l) to gate(h) delay gate(l)<2v, gate(h)>2v 30 65 100 ns gate pull-down resistance to pgnd (note 1) 20 50 115 k ? v core overcurrent protection ovc comparator offset voltage 0v < v out1 3.5v 77 86 101 mv discharge threshold voltage 0.2 0.25 0.3 v v out1 bias current 0.2v v out1 3.5v -7.0 0.1 7.0 a ovc latch discharge current v comp = 1v 100 800 2500 a pwm comparator 1 pwm comparator offset voltage 0v v ffb1 3.5v 0.95 1.06 1.18 v transient response v ffb1 = 0 to 3.5v 200 300 ns v ffb1 bias current 0.2v v ffb1 3.5v -7.0 0.1 7.0 a c off1 off-time 1.0 1.6 2.3 s charge current v coff1 = 1.5v 550 a discharge current v coff1 = 1.5v 25 ma power-good output pwrgd sink current v fb1 = 1.7v, v pwrgd = 5v 0.5 4 15 ma pwrgd upper threshold % of nominal dac code 5 8.5 12 % pwrgd lower threshold % of nominal dac code -12 -8.5 -5 % pwrgd output low voltage v fb1 = 1.7v, i pwrgd = 500a 0.2 0.3 v overvoltage protection (ovp) output ovp source current ovp = 1v 1 10 25 ma ovp threshold % of nominal dac code 5 8.5 12 % ovp pull-up voltage i ovp = 1ma, v cc1 - v ovp 1.1 1.5 v v i/o switching regulator error amplifier v fb2 bias current v fb2 = 0v -1.0 0.1 1.0 a comp2 source current comp2 = 1.2v to 3.6v; v fb2 = 1v 15 30 60 a comp2 sink current comp2=1.2v; v fb2 =1.4v; 30 60 120 a open loop gain c comp2 = 0.1f 80 db
cs5132h parameter test conditions min typ max unit electrical characteristics: 0? < t a < 70?; 0? < t j < 125?; v out2 3.5v, 9v v cc1 14v, 9v v cc2 20v; 2.0v dac code (v id4 = v id3 = v id2 = v id1 = 0, v id0 = 1), c gate(h) = c gate(l) = c gate = 3.3nf, c off = 390pf; unless otherwise stated. 6 v i/o switching regulator error amplifier continued unity gain bandwidth c comp2 = 0.1f 20 khz psrr @ 1khz c comp2 = 0.1f 70 db reference voltage v fb2 =comp2 1.205 1.230 1.255 v gate high voltage at 100ma measure v cc2 ?ate 1.2 2.1 v low voltage at 100ma measure gate 1.0 1.5 v rise time 1.6v < gate < (v cc2 ?2.5v) 40 80 ns fall time (v cc2 ?2.5v) > gate > 1.6v 40 80 ns gate pull-down resistance to pgnd 20 50 115 k ? v i/o overcurrent protection ovc2 comparator offset voltage 0v < v out2 3.5v 77 86 101 mv discharge threshold voltage 0.2 0.25 0.3 v v out2 bias current 0.2v v out2 3.5v -7.0 0.1 7.0 a ovc2 latch discharge current 100 800 2500 a pwm comparator 2 pwm comparator offset voltage 0v v ffb2 3.5v 0.99 1.10 1.22 v transient response v ffb2 = 0 to 3.5v 200 300 ns v ffb2 bias current 0.2v v ffb2 3.5v -7.0 0.1 7.0 a c off2 off-time 1.0 1.6 2.3 s charge current v coff2 = 1.5v 550 a discharge current v coff2 = 1.5v 25 ma general electrical specifications v cc monitor start threshold all outputs on 7.9 8.4 8.9 v v cc monitor stop threshold all outputs off 7.6 8.1 8.6 v hysteresis start - stop 0.15 0.30 0.60 v v cc1 supply current no load on gate(l) 13 20 ma v cc2 supply current no loads on gate(h) and gate 6 9 ma note 1: guaranteed by design, not 100% tested in production.
v 2 tm control method the v 2 tm method of control uses a ramp signal that is gen- erated by the esr of the output capacitors. this ramp is proportional to the ac current through the main inductor and is offset by the value of the dc output voltage. this control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is gen- erated from the output voltage itself. this control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. figure 1: v 2tm control diagram. the v 2 tm control method is illustrated in figure 1. the out- put voltage is used to generate both the error signal and the ramp signal. since the ramp signal is simply the output voltage, it is affected by any change in the output regard- less of the origin of that change. the ramp signal also con- tains the dc portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. a change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the v 2 tm control scheme to compensate the duty cycle. since the change in inductor current modifies the ramp signal, as in current mode control, the v 2 tm control scheme has the same advantages in line transient response. a change in load current will have an affect on the output voltage, altering the ramp signal. a load step immediately changes the state of the comparator output, which controls the main switch. load transient response is determined only by the comparator response time and the transition speed of the main switch. the reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. the error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. the main purpose of this ?low?feedback loop is to provide dc accuracy. noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effective- ly filtered. line and load regulation are drastically improved because there are two independent voltage loops. a voltage mode controller relies on a change in the error signal to compen- sate for a deviation in either line or load voltage. this change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. a current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. the v 2 tm method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load. constant off-time to minimize transient response, the cs5132h uses a constant off-time method to control the rate of output pulses. during normal operation, the off-time of the high side switch is terminated after a fixed period, set by the c off capacitor. every time the v ffb pin exceeds the comp pin voltage an off-time is initiated. to maintain regula- tion, the v 2 tm control loop varies switch on-time. the pwm comparator monitors the output voltage ramp, and terminates the switch on-time. constant off-time provides a number of advantages. switch duty cycle can be adjusted from 0 to 100% on a pulse-by pulse basis when responding to transient condi- tions. both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line transients. programmable output the cs5132h is designed to provide two methods for pro- gramming the output voltage of the power supply. a five bit on board digital to analog converter (dac) is used to program the output voltage within two different ranges. the first range is 2.125v to 3.525v in 100mv steps, the sec- ond is 1.325v to 2.075v in 50mv steps, depending on the digital input code. if all five bits are left open, the cs5132h enters adjust mode. in adjust mode, the designer can choose any output voltage by using resistor divider feed- back to the v fb pin, as in traditional controllers. the cs5132h is specifically designed to meet or exceed intel? pentium ii specifications. error amplifier an inherent benefit of the v 2 tm control topology is that there is no large bandwidth requirement on the error amplifier design. the reaction time to an output load step has no relation to the crossover frequency, since transient response is handled by the ramp signal loop. the main purpose of this?low?eedback loop is to provide dc accu- racy. noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low fre- quency. enhanced noise immunity improves remote sens- ing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. the comp pin is the output of the error amplifier and a capacitor to lgnd compensates the error amplifier loop. additionally, through the built-in offset on the pwm comparator non- inverting input, the comp pin provides the hiccup timing for the over-current protection, the soft start function that reference voltage + c e + ramp signal output voltage feedback error signal gate(h) gate(l) error amplifier comp pwm comparator v ffb v fb theory of operation application information 7 cs5132h
minimizes inrush currents during regulator power-up, and switcher output enable. start-up the cs5132h provides a controlled start-up of regulator output voltage and features programmable soft start imple- mented through the error amp and external compensation capacitor. this feature, combined with overcurrent protec- tion, prevents stress to the regulator power components and overshoot of the output voltage during start-up. as power is applied to the regulator, the cs5132h undervoltage lockout circuit (uvl) monitors the ics sup- ply voltage (v cc ) which is typically connected to the +12v output of the ac-dc power supply. the uvl circuit pre- vents the nfet gates from being activated until v cc exceeds the 8.4v (typ) threshold. hysteresis of 300mv (typ) is provided for noise immunity. the error amp capacitor connected to the comp pin is charged by a 30a current source. this capacitor must be charged to 1.06v (typ) so that it exceeds the pwm comparator? offset before the v 2 pwm control loop will permit switching to occur. when v cc has exceeded 8.4v and comp has charged to 1.06v, the upper gate driver (gate(h)) is activated, turn- ing on the upper fet. this causes current to flow through the output inductor and into the output capacitors and load according to the following equation: i = (v in ?v out ) x gate(h) and the upper nfet remain on and inductor cur- rent ramps up until the initial pulse is terminated by either the pwm control loop or the overcurrent protection. this initial pulse of in-rush current minimizes start-up time, but does not overstress the regulator? power components. the pwm comparator will terminate the initial pulse if the regulator output exceeds the voltage on the comp pin minus the 1.06v pwm comparator offset prior to the drop across the current sense resistor exceeding the current limit threshold. in this case, the pwm control loop has achieved regulation and the initial pulse is then followed by a con- stant off time as programmed by the c off capacitor. the comp capacitor will continue to slowly charge and regula- tor output voltage will follow it, less the 1.06v pwm offset, until it achieves the voltage programmed by the dac? vid input. the error amp will then source or sink current to the comp cap as required to maintain the correct regulator dc output voltage. since the rate of increase of the comp pin voltage is typically set much slower than the regulator? slew capability, inrush current, output voltage, and duty cycle all gradually increase from zero. (see figures 2, 3, and 4.) if the voltage across the current sense resistor generates a voltage difference between the v ffb and v out pins that exceeds the ovc comparator offset voltage (86mv typi- cal), the fault latch is set. this causes the comp pin to be quickly discharged, turning off gate(h) and the upper nfet since the voltage on the comp pin is now less than the 1.06v pwm comparator offset. the fault latch is reset when the voltage on the comp decreases below the discharge threshold voltage (0.25v typical). the comp capacitor will again begin to charge, and when it exceeds the 1.06v pwm comparator offset, the regulator output will softstart normally (see figure 5). because the start-up circuitry depends on the current sense function, a current sense resistor should always be used. figure 2: normal start-up (2ms/div). channel 1 - regulator output voltage (1v/div) channel 2 - comp pin (1v/div) channel 3 - v cc (10v/div) channel 4 - regulator input voltage (5v/div) figure 3: normal start-up showing initial pulse followed by soft start (20s/div). channel 1 - regulator output voltage (0.2v/div) channel 2 ?inductor switching node (5v/div) channel 3 - v cc (10v/div) channel 4 - regulator input voltage (5v/div) start-up @ v cc > 8.4v initial pulse until v out > comp - pwm offset start-up @ v cc > 8.4v t l application information: continued 8 cs5132h
figure 4: pulse-by-pulse regulation during soft start (2s/div). channel 1 - regulator output voltage (0.2v/div) channel 2 ?inductor switching node (5v/div) channel 3 - v cc (10v/div) channel 4 - regulator input voltage (5v/div) figure 5: start-up with comp pre-charged to 2v (2ms/div). channel 1 - regulator output voltage (1v/div) channel 2 - comp pin (1v/div) channel 3 - v cc (10v/div) channel 4 - regulator input voltage (5v/div) when driving large capacitive loads, the comp must charge slowly enough to avoid tripping the cs5132h over- current protection. the following equation can be used to ensure unconditional start-up. < where i chg = comp source current (30a typical); c comp = comp capacitor value (0.1f typical); i lim = current limit threshold; i load = load current during start-up; c out = total output capacitance. normal operation during normal operation, switch off-time is constant and set by the c off capacitor. switch on-time is adjusted by the v 2 tm control loop to maintain regulation. this results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. output voltage ripple will be determined by inductor rip- ple current and the esr of the output capacitors transient response the cs5132h v 2 tm control loop? 200ns reaction time pro- vides unprecedented transient response to changes in input voltage or output current. pulse-by-pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. overall load transient response is further improved through a feature called ?daptive voltage positioning? this tech- nique pre-positions the output voltage to reduce total out- put voltage excursions during changes in load. holding tolerance to 1% allows the error amplifiers refer- ence voltage to be targeted +25mv high without compro- mising dc accuracy. a ?roop resistor? implemented through a pc board trace, connects the error amps feed- back pin (v fb ) to the output capacitors and load and carries the output current. with no load, there is no dc drop across this resistor, producing an output voltage tracking the error amps, including the +25mv offset. when the full load current is delivered, a 50mv drop is developed across this resistor. this results in output voltage being offset - 25mv low. the result of adaptive voltage positioning is that addition- al margin is provided for a load transient before reaching the output voltage specification limits. when load current suddenly increases from its minimum level, the output is pre-positioned +25mv. conversely, when load current sud- denly decreases from its maximum level, the output is pre- positioned -25mv. for best transient response, a combina- tion of a number of high frequency and bulk output capaci- tors are usually used. slope compensation the v 2 tm control method uses a ramp signal, generated by the esr of the output capacitors, that is proportional to the ripple current through the inductor. to maintain regula- tion, the v 2 tm control loop monitors this ramp signal, through the pwm comparator, and terminates the switch on-time. the stringent load transient requirements of modern micro- processors require the output capacitors to have very low esr. the resulting shallow slope presented to the pwm comparator, due to the very low esr, can lead to pulse width jitter and variation caused by both random or syn- chronous noise. i lim ?i load c out i chg c comp soft start @ comp > 1.06v ocp @ v cc > 8.5v duty cycle = v out / v in 0.27v / 3.54v = 7% 5.2% application information: continued 9 cs5132h
adding slope compensation to the control loop, avoids erratic operation of the pwm circuit, particularly at lower duty cycles and higher frequencies, where there is not enough ramp signal, and provides a more stable switch- point. the scheme that prevents that switching noise prematurely triggers the pwm circuit consists of adding a positive volt- age slope to the output of the error amplifier (comp pin) during an off-time cycle. the circuit that implements this function for the syn- chronous regulator section (v cc(core) ) is shown in figure 6. figure 6: small rc filter provides the proper voltage ramp at the begin- ing of each on-time cycle. the ramp waveform is generated through a small rc filter that provides the proper voltage ramp at the beginning of each on-time cycle. the resistors r 1 and r 2 in the circuit of figure 6 form a voltage divider from the gate(l) output, superimposing a small artificial ramp on the output of the error amplifier. a similar approach can be used also for the non-syn- chronous regulator section (v i/o ) as shown in figure 7. in this case, the slope compensation signal is generated direct- ly from the gate output, through the ac coupling capaci- tor c 1 , at the beginning of each on-cycle. it is important that in both circuits, the series combination r 1 /r 2 is high enough in resistance not to load down and negatively affect the slew rate on the gate(l) and gate pins. figure 7: slope compensation for the non-synchronous regulator section (v i/o ). over-current protection a loss-less hiccup mode current limit protection feature is provided, requiring only the comp capacitor to imple- ment. the cs5132h provides overcurrent protection by sensing the current through a ?roop?resistor, using an internal current sense comparator. the comparator com- pares the voltage drop across the ?roop?resistor to an internal reference voltage of 86mv (typical). if the voltage drop across the ?roop?resistor exceeds this threshold, the current sense comparator allows the fault latch to be set. this causes the regulator to stop switching. during this over current condition, the cs5132h stays off for the time it takes the comp pin capacitor to discharge to its lower 0.25v threshold. as soon as the comp pin reaches 0.25v, the fault latch is reset (no overcurrent condition pre- sent) and the comp pin is charged with a 30a current source to a voltage 1.06v greater than the v ffb voltage. only at this point the regulator attempts to restart normal- ly. the cs5132h will operate initially with a duty cycle whose value depends on how low the v ffb voltage was during the overcurrent condition (whether hiccup mode was due to excessive current or hard short). this protection scheme minimizes thermal stress to the regulator compo- nents, input power supply, and pc board traces, as the over current condition persists. upon removal of the overload, the fault latch is cleared, allowing normal operation to resume. overvoltage protection overvoltage protection (ovp) is provided as result of the normal operation of the v 2 tm control topology and requires no additional external components. the control loop responds to an overvoltage condition within 200ns, causing the top mosfet to shut off, disconnecting the regulator from its input voltage. this results in a ?rowbar?action to clamp the output voltage and prevents damage to the load. the regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. additionally, a dedicated overvoltage protection (ovp) output pin (pin 21) is provided in the cs5132h. the ovp signal will go high (overvoltage condition), if the output voltage (v cc(core) ) exceeds the regulation voltage by 8.5% of the voltage set by the particular dac code. the ovp pin can source up to 25ma of current that can be used to drive an scr to crowbar the power supply. power-good circuit the power-good pin (pin 22) is an open-collector signal consistent with ttl dc specifications. it is externally pulled up, and is pulled low (below 0.3v) when the regula- tor output voltage typically exceeds 8.5% of the nominal output voltage. maximum output voltage deviation before power-good is pulled low is 12%. output enable on/off control of the regulator outputs can be implement- ed by pulling the comp pins low. it is required to pull the comp pins below the 1.06v pwm comparator offset volt- age in order to disable switching on the gate drivers. protection and monitoring features r 1 c 1 15 13 gate comp2 cs5132h to v i/o power switch c comp2 r 2 c comp r 1 to synchronous fet c 1 r 2 5 19 comp1 gate(l) cs5132h application information: continued 10 cs5132h
step 1: define specification input voltage from ?ilver box?power supply ?5v 5% for conversion to output voltage ?12v 5% for nfet gate voltage and circuit bias output voltages ?2.0v @ 16a for v cc(core) ?3.3v@ 8a for v i/o ?5% overall voltage accuracy (load, line, temperature, ripple) ?2% dc & 5% ac voltage accuracy ?< 2% output ripple voltage ?15a load step @ 20a /s - v cc(core) ?7a load step @ 5a/s - v i/o thermal management ?0 to 50 c ambient temperature range ?component junction temperatures within manufactur- er? specified ratings at full load & t a(max) components ?low cost is top priority. ?surface mount when possible ?small footprint important ?component ratings determined at 80% of maximum load step 2: determine output capacitors these components must be selected and placed carefully to yield optimal results. capacitors should be chosen to pro- vide acceptable ripple on the regulator output voltage. key specifications for input capacitors are their ripple rating, while esr is important for output capacitors. for best tran- sient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. step 2a: for the 2v output (v cc(core) ) the load transients have slew rates of up to 20a /s, while the voltage drop during a transient must be kept to less than 100mv. the output capacitors must hold the output voltage within these limits since the inductor current can not change with the required slew rate. the output capaci- tors must therefore have a very low esl and esr. the voltage transient during the load step is ? v out = ? i out ( + esr + ) , where t tr = output voltage transient response time. the total change in output voltage is divided as follows: esr - 80mv esl - 10mv output capacitor discharge during transient - 10mv maximum allowable esr is: esr = = 5.3m ? . the esr for a 1200f/10v sanyo capacitor type gx is 44m ? per capacitor. number of capacitors = ? 8. total esr = = 5.5m ? . output voltage deviation due to esr: ? v = 15a 5.5m ? = 82mv. the esl is calculated from = , esl = = = 0.5nh. it is estimated that a 10 12 mm aluminum electrolytic capacitor has approximately 4nh of package inductance. in this case we have eight (8) capacitors in parallel for a total capacitor esl: esl = = 0.5nh. output voltage deviation due to esl: ? v = = = 10mv. the change in capacitor voltage during the transient is: ? v c =, where t tr is the output voltage transient response time. we choose t tr = 6s: ? v c = = 9mv. total change in output voltage as a result of an increase in load current of a 15a step with a 20a/s slew rate is: ? v out = ( 82mv + 10mv + 9mv ) = 101mv. step 2b: for the 3.3v output (v i/o ) the v i/o load transients have slew rates of 5a/s, while the voltage drop during a transient must be kept to less 15a 6 ? 8 1200 ? ? i t tr c out 0.5nh 20a 1s esl ? i ? t 4 n 8 0.01v 1 10 ?6 20 ? v ? t ? i 20a ? ? i ? t 44 8 44 5.3 0.08v 15a t tr c out esl ? t cs5132h-based dual output buck regulator design example application information: continued 11 cs5132h
than 165mv. repeating step 2a, we select four (4) 1200f/10v sanyo gx output capacitors. step 3: duty cycle, switching frequency, t on & t off duty cycle v out / v in. d = 2.0v / 5v = 40% for 2v output. d = 3.3v / 5v = 66% for 3.3v output. select 200khz switching frequency (f sw ). step 3a: calculate on-time for 2v output t on = = = 2s calculate off-time: t off = = 5s - 2s = 3s. select the c off1 capacitor in order to set the off-time: c off1 = = = 750pf. a standard c off1 capacitance value of 680pf can be used. the 3980 factor is a characteristic of the cs5132h. step 3b: calculate on-time for 3.3v output t on = = = 3.3s calculate off-time: t off = - t on = 5s ?3.3s = 1.7s. select c off2 to be 390pf. step 4: output inductor the inductor should be selected based on its inductance, current capability, and dc resistance. increasing the induc- tor value will decrease output voltage ripple, but degrade transient response. there are many factors to consider in selecting the inductor including: cost, efficiency, emi and ease of manufacture. the inductor must be able to handle the peak current at the switching frequency without satu- rating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. there are a variety of materials and types of magnetic cores that could be used for this application. among them are: ferrites, molypermalloy cores (mpp), amorphous and powdered iron cores. we will use a powdered iron core. iron powdered cores are very suitable due to their high sat- uration flux density and have low loss at high frequencies, a distributed gap and exhibit very low emi. calculate inductor value: l= = = =1.2h. step 4a: select 2% ripple on 2v output ? v out = 2% 2v = 40mv the maximum allowable inductor ripple current for a 2% ripple on the 2v output is: ? i l = = = 7.3a, which corresponds to the following maximum inductor peak and valley currents: i l(peak) = i out + () = 16a + () = 19.6a, i l(valley) = i out - () = 16a - () = 12.4a. the selected 1.2h inductor yields the following ripple current: ? i l = = = 5a. the maximum inductor peak current becomes: i l(peak) = 16a + = 16a + 2.5a = 18.5a. the inductor valley current becomes: i l(valley) = 16a - = 16a - 2.5a = 13.5a. the above values are well within the maximum allowable inductor peak and valley currents for a 2% output voltage ripple. select toroid powdered iron core, low cost, low core loss- es at 200khz, low emi. select xfmrs inc, xf0016-vo4 1.2h inductor with r dc = 0.003 ? typical, 0.008 ? maximum. step 4b: select 2% ripple on 3.3v output repeating step 4a for the 3.3v output, we find 3.5h is a suitable value for this output. step 5: input capacitors these components must be selected and placed carefully to yield optimal results. capacitors should be chosen to pro- vide acceptable ripple on the input supply lines. key speci- fications for input capacitors are their ripple rating. step 5a: v cc(core) buck regulator input capacitors the input capacitor c in should also be able to handle the 5a 2 5a 2 (5v - 2v) 0.4 200khz 1.2h (v in - v out ) d f sw l 7.3a 2 ? i l 2 7.3a 2 ? i l 2 40mv 5.5m ? ? v out total esr 3v 6s 15a (5v-2v) 6s 15a (v in - v out ) t tr ? i 1 f sw 0.66 200khz d f sw 5s 0.6 3980 period (1-d) 3980 - t on 1 f sw 0.40 200khz d f sw application information: continued 12 cs5132h
input rms current i in(rms) . c in discharges during the on- time. the discharge current is given by: i cindisrms = = 10.2a. c in charges during the off-time, the average current through the capacitor over one switching cycle is zero: i cin(ch) = i cin(dis) , i cin(ch) = 10.2a = 6.8a. so the total input rms current is: i cin(rms) = (i cin(dis) 2 d) +( i cin(ch) 2 (1-d) ), i cin(rms) = . the number of input capacitors required is given by: n cin =. for sanyo capacitors type gx: 1200f/10v , i ripple = 1.25a. hence, n cin = = 6.6. the number of input capacitors can be rounded off to 6. calculate the input capacitor ripple voltage: v rms = i rms total esr = 8.3a 7.3m ? = 60mv. calculate the input capacitor power loss: p cin = i rms 2 total esr = 0.504w. step 5b: v i/o buck regulator input capacitors repeating for the 3.3v output, we select 3 gx 1200f/10v capacitors. step 6: power mosfets fet basics the use of the mosfet as a power switch is propelled by two reasons: 1) its very high input impedance and 2) its very fast switching times. the electrical characteristics of a mosfet are considered to be those of a perfect switch. control and drive circuitry power is therefore reduced. because the input impedance is so high, it is voltage driv- en. the input of the mosfet acts as if it were a small capacitor, which the driving circuit must charge at turn on. the lower the drive impedance, the higher the rate of rise of v gs , and the faster the turn- on time. power dissipation in the switching mosfet consists of 1) conduction losses, 2) leakage losses, 3) turn-on switching losses, 4) turn-off switching losses, and 5) gate-transitions losses. the latter three losses are proportional to frequency. for the conduct- ing power dissipation rms values of current and resistance are used for true power calculations. the fast switching speed of the mosfet makes it indis- pensable for high-frequency power supply applications. not only are switching power losses minimized, but the maximum usable switching frequency is considerably higher. switching time is independent of temperature. also, at higher frequencies, the use of smaller and lighter components (transformer, filter choke, filter capacitor) reduces overall component cost while using less space for more efficient packaging at lower weight. the mosfet has purely capacitive input impedance. no dc current is required. it is important to keep in mind the drain current of the fet has a negative temperature coeffi- cient. increase in temperature causes higher on-resistance and greater leakage current. for switching circuits, v ds(on) should be low to minimize power dissipation at a given i d , and v gs should be high to accomplish this. mosfet switching times are determined by device capacitances, stray capacitances, and the impedance of the gate drive circuit. thus the gate driving circuit must have high momentary peak current sourcing and sinking capability for switching the mosfet. the input capacitance, output capacitance and reverse-transfer capacitance also increase with increased device current rating. two considerations complicate the task of estimating switching times. first, since the magnitude of the input capacitance, c iss , varies with v ds , the rc time constant determined by the gate-drive impedance and c iss changes during the switching cycle. consequently, computation of the rise time of the gate voltage by using a specific gate- drive impedance and input capacitance yields only a rough estimate. the second consideration is the effect of the "miller" capacitance, c rss , which is referred to as c dg in the following discussion. for example, when a device is on, v ds is fairly small and v gs is about 12v. c dg is charged to v ds(on) - v gs , which is a negative potential if the drain is considered the positive electrode. when the drain is "off", c dg is charged to quite a different potential. in this case the voltage across c dg is a positive value since the potential from gate-to-source is near zero volts and v ds is essentially the drain supply voltage. during turn-on and turn-off, 8.3 1.25 i cin(rms) i ripple (10.2 2 0.4 ) + (6.8 2 ( 0.6 )) = 8.3a 0.4 (1-0.4) d 1-d (i l(peak) 2 + (i l(peak) i l(valley) ) + i l(valley 2 ) d 3 application information: continued 13 cs5132h
these large swings in gate-to-drain voltage tax the current sourcing and sinking capabilities of the gate drive. in addi- tion to charging and discharging c gs , the gate drive must also supply the displacement current required by c dg (i gate = c dg dv dg /dt). unless the gate-drive impedance is very low, the v gs waveform commonly plateaus during rapid changes in the drain-to-source voltage. the most important aspect of fet performance is the static drain-to-source on-resistance (rds on ), which effects regulator efficiency and fet thermal management require- ments. the on- resistance determines the amount of cur- rent a fet can handle without excessive power dissipation that may cause overheating and potentially catastrophic failure. as the drain current rises, especially above the con- tinuous rating, the on-resistance also increases. its posi- tive temperature coefficient is between +0.6%/c and +0.85 %/c. the higher the on-resistance the larger the conduction loss is. both logic level and standard fets can be used. the refer- ence designs derive gate drive from the 12v supply which is generally available in most computer systems and uti- lizes logic level fets. multiple fets may be paralleled to reduce losses and improve efficiency and thermal manage- ment. voltage applied to the fet gates depends on the applica- tion circuit used. both upper and lower gate driver outputs are specified to drive to within 1.5v of ground when in the low state and to within 2v of their respective bias supplies when in the high state. in practice, the fet gates will be driven rail-to-rail due to overshoot caused by the capaci- tive load they present to the controller ic. we select mitsubishi? fs70vsj-03 (d 2 package): 30v withstand voltage; rds on = 8m ? ; ja = 40?/w; total gate charge = 50nc. step 6a: for the 2v output upper (switching) fet calculate the 2v output? maximum rms current through the switch: i rms(h) = = 10.2a. calculate switch conduction losses: p rms = i rms 2 rds on = 10.2a 2 8m ? = 0.83w. calculate switching losses: switch on losses: p sw(on) = , t rise = 60ns, (from mitsubishi fs70vsj-03 switching characteristics per- formance curves): t = = 5s, p sw(on) = = 0.16w. switch off losses: p sw(off) = , t fall = 160ns, (from mitsubishi fs70vsj-03 switching characteristics per- formance curves): p sw(off) = = 0.43w. upper fet total losses = switching conduction losses + switch on losses + switch off losses: p feth(total) = 0.83w + 0.16w + 0.43w = 1.42w. calculate maximum nfet switch junction temperature: t j = t a + [(p feth(total) ) ja ], t j = 50c + (1.412w) 40?/w = 107?. calculate the gate driver losses: p gate(h) = q v gate f sw = 50nc 12v 200khz = 120mw. step 6b: similar calculations apply for the 3.3v output. step 6c: synchronous fet ( 2v output) calculate switch conduction losses: p rms = i rms 2 rds on = [i out 2 (1-d)] rds on = [16a 2 0.6] 8m ? = 1.22w. the synchronous mosfet has no switching losses, except for losses in the internal body diode, because it turns on into near zero voltage conditions. the mosfet body diode will conduct during the non-overlap time and the resulting power dissipation (neglecting reverse recovery losses) can be calculated as follows: p sw = v sd i load non-overlap time switching frequency. from the mitsubishi fs70vsj-03 source-drain diode for- ward characteristics curve, v sd = 0.8v: p sw = 0.8v 16a 65ns 200khz, p sw = 0.16w. 5v 16a 160 10 -9 6 5 10 -6 v in i out t fall 6t 5v 16a 60 10 -9 6 5 10 -6 1 f sw (v in i out t rise ) 6t (i l(peak) 2 + (i l(peak) i l(valley) ) + i l(valley 2 ) d 3 application information: continued 14 cs5132h
lower (synchronous) fet total losses = switch conduc- tion losses + body diode losses: p fetl(total) = 1.27w + 0.16w =1.43w. calculate maximum nfet switch junction temperature: t j = t a + [(p fetl(total) ) ja ], t j = 50c + (1.43w) 40?/w = 107?. calculate the gate driver losses: p gate(l) = q v gate f sw = 50nc 12v 200khz = 120mw. step 7: free wheeling schottky diode (3.3v output) the four most application-important characteristics of a schottky are: 1. forward voltage drop; 2. reverse leakage current; 3. reverse blocking voltage; 4. maximum permissible junction temperature. we calculate the average schottky current: i avg = i out (1? d ) = 8 0.34 = 2.72. we select the motorola mbrd835l rated at 8a, with 35v dc blocking voltage and 0.51vforward voltage drop. neglecting reverse losses, the power dissipation is due to the conduction loss only and can be computed as follows: p schottky = v f i avg , where v f = maximum instantaneous forward voltage; p schottky = 0.51v 2.72 = 1.39 w. calculate maximum schottky junction temperature: t j = t a + [(p schottky ) ja ], t j = 50c + (1.39w 80?/w) = 161?. proper heatsinking (copper pad under schottky) will be required to reduce schottky t j below +125?. step 8: ic power dissipation the power dissipation on the ic varies with the mosfets used, v cc and the cs5132h operating frequency. this power dissipation is typically dominated by the average gate charge current for the mosfets. the average current is approximately: i d = (q gate(h) + q gate(l) ) f sw1 + q gate f sw2 , where i d = average drive current; q gate(x) = total gate charge for each mosfet; f sw1 , f sw2 = switching frequencies for the synchronous and non-synchronous sections respectively. the power dissipation for the ic when v cc1 = v cc2 = v cc is: p d = i cc v cc + i d v cc , where i cc = quiescent supply current of the ic (both from v cc1 and v cc2 ). for the design example in question, p d = 19ma 12v + 0.12w + 0.12w + 0.12w = 0.59w. the junction temperature of the ic is primarily a function of the pcb layout, since most of the heat is removed through the traces connected to the pins of the ic. adaptive voltage positioning is used to help keep the out- put voltage within specification during load transients. to implement adaptive voltage positioning a ?roop resistor?must be connected between the output inductor and output capacitors and load. this resistor carries the full load current and should be chosen so that both dc and ac tolerance limits are met. an embedded pc trace resis- tor has the distinct advantage of near zero cost implemen- tation. however, this droop resistor can vary due to three reasons: 1) the sheet resistivity variation caused by varia- tion in the thickness of the pcb layer; 2) the mismatch of l/w; and 3) temperature variation. 1) sheet resistivity for one ounce copper, the thickness variation is typically 1.26 mil to 1.48 mil. therefore the error due to sheet resis- tivity is: = 8%. 2) mismatch due to l/w the variation in l/w is governed by variations due to the pcb manufacturing process. the error due to l/w mis- match is typically 1%. 3) thermal considerations due to i 2 r power losses the surface temperature of the droop resistor will increase causing the resistance to increase. also, the ambient temperature variation will con- tribute to the increase of the resistance, according to the formula: r = r 20 [1+ 20 (?20)], 1.48 - 1.26 1.37 ?roop?resistor for adaptive voltage positioning and current limit application information: continued 15 cs5132h
where r 20 = resistance at 20?; = ; t = operating temperature; r = desired droop resistor value. for temperature t = 50?, the % r change = 12%. droop resistor tolerance tolerance due to sheet resistivity variation 8% tolerance due to l/w error 1% tolerance due to temperature variation 12% total tolerance for droop resistor 21% in order to determine the droop resistor value the nominal voltage drop across it at full load has to be calculated. this voltage drop has to be such that the output voltage at full load is above the minimum dc tolerance spec: v droop(typ) = . example: for a 450mhz pentium ii, the dc accuracy spec is 1.93 < v cc(core) < 2.07v, and the ac accuracy spec is 1.9v < v cc(core) < 2.1v. the cs5132h dac output voltage is +2.004v < v dac < +2.045v. in order not to exceed the dc accuracy spec, the voltage drop developed across the resis- tor must be calculated as follows: v droop(typ) = = = 61mv. with the cs5132h dac accuracy being 1%, the internal error amplifier? reference voltage is trimmed so that the output voltage will be 25mv high at no load. with no load, there is no dc drop across the resistor, producing an out- put voltage tracking the error amplifier output voltage, including the offset. when the full load current is deliv- ered, a drop of -50mv is developed across the resistor. therefore, the regulator output is pre-positioned at 25mv above the nominal output voltage before a load turn-on. the total voltage drop due to a load step is ? v-25mv and the deviation from the nominal output voltage is 25mv smaller than it would be if there was no droop resistor. similarly at full load the regulator output is pre-positioned at 25mv below the nominal voltage before a load turn-off. the total voltage increase due to a load turn-off is ? v-25mv and the deviation from the nominal output voltage is 25mv smaller than it would be if there was no droop resistor. this is because the output capacitors are pre-charged to a value that is either 25mv above the nominal output voltage before a load turn-on or, 25mv below the nominal output voltage before a load turn-off . obviously, the larger the voltage drop across the droop resistor (the larger the resistance), the worse the dc and load regulation, but the better the ac transient response. current limit the current limit setpoint has to be higher than the normal full load current. attention has to be paid to the current rating of the external power components as these are the first to fail during an overload condition. the mosfet continuous and pulsed drain current rating at a given case temperature has to be accounted for when setting the cur- rent limit trip point. temperature curves on mosfet manufacturers?data sheets allow the designer to determine the mosfet drain current at a particular v gs and t j (junction temperature). this, in turn, will assist the designer to set a proper current limit, without causing device breakdown during an over- load condition. for future ?pus?the full load will be 16a. the internal current sense comparator current limit voltage limits are: 77mv < v th < 101mv. also, there is a 21% total variation in r sense as discussed in the previous section. we compute the value of the current sensing element (embedded pcb trace) for the minimum current limit set- point: r sense(min) = r sense(typ) 0.79, r sense(max) = r sense(typ) 1.21, r sense(max) = = = 4.8m ? . we select, r sense(typ) = 3.3m ? . we calculate the range of load currents that will cause the internal current sense comparator to detect an overload condition. nominal current limit setpoint from the overcurrent detection data in the electrical char- acteristics table: v th(typ) = 86mv, i cl(nom) = = = 26a. maximum current limit setpoint from the overcurrent detection data in the electrical char- acteristics table: v th(max) = 101mv, i cl(max) == = = 38.7a. 101mv 3.3m ? 0.79 v th(max) r sense(nom) 0.79 v th(max) r sense(min) 86mv 3.3m ? v th(typ) r sense(nom) 77mv 16a v th(min) i cl(min) +2.004v-1.93v 1.21 [v dac(min) -v dc (min) ] 1+r droop(tolerance) v dac(min) -v dc(min) 1+r droop(tolerance) 0.00393 ? 16 application information: continued cs5132h
application information: continued therefore, the range of load currents that will cause the internal current sense comparator to detect an overload condition through a 3.3m ? embedded pcb trace is: 19.3a < i cl < 38.7a, with 26a being the nominal overload condi- tion. design rules for using a droop resistor the basic equation for laying an embedded resistor is: r ar = or r = , where a= w t = cross-sectional area; = the copper resistivity ( ? -mil); l= length (mils); w = width (mils); t = thickness (mils). for most pcbs the copper thickness, t, is 35m (1.37 mils) for one ounce copper; = 717.86 ? -mil. for a cpu load of 16a the resistance needed to create a 50mv drop at full load is: r droop = = = 3.1m ? . the resistivity of the copper will drift with the temperature according to the following guidelines: ? r = 12% @ t a = +50?; ? r = 34% @t a = +100?. droop resistor length, width, and thickness the minimum width and thickness of the droop resistor should primarily be determined on the basis of the current- carrying capacity required, and the maximum permissible droop resistor temperature rise. pcb manufacturer design charts can be used in determining current- carrying capaci- ty and sizes of etched copper conductors for various tem- perature rises above ambient. for single conductor applications, such as the use of the droop resistor, pcb design charts show that for a droop resistor with a required current-carrying capacity of 16a, and a 45? temperature rise above ambient, the recom- mended cross section is 275 mil 2 . w t = 275 mil 2 , where w = droop resistor width; t = droop resistor thickness. for 1oz. copper, t= 1.37 mils, therefore w = 201 mils = 0.201 in. r = ? , where r = droop resistor value; = 0.71786m ? -mil (1 oz. copper); l = droop resistor length; w = droop resistor width. r droop = 3.3m ?. 3.3m ? = 0.71786m ? -mil . hence, l = 1265 mils = 1.265 in. in layouts where it is impractical to lay out a droop resistor in a straight line 1265 mils long, the embedded pcb trace can be ?naked?to fit within the available space. thermal considerations for power mosfets and diodes in order to maintain good reliability, the junction tempera- ture of the semiconductor components should be kept to a maximum of 150? or lower. the thermal impedance (junction to ambient) required to meet this requirement can be calculated as follows: thermal impedance = . a heatsink may be added to to-220 components to reduce their thermal impedance. a number of pc board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components. as a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. when designing for compliance with emi/emc regulations, additional components may be added to reduce noise emissions. these components are not required for regulator operation and experimental results may allow them to be eliminated. the input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. placement of the power component to minimize routing distance will also help to reduce emissions. emi management t j(max) - t a power thermal management l 201 mils 1.37 mils l w t 50mv 16a 50mv i out l (w t) l a 17 cs5132h
18 application information: continued cs5132h when laying out the cpu buck regulator on a printed cir- cuit board, the following checklist should be used to ensure proper operation of the cs5132h. 1) rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. 2) keep high currents out of sensitive ground connections. avoid connecting the ic gnd between the source of the lower fet and the input capacitor gnd. 3) avoid ground loops as they pick up noise. use star or single point grounding. 4) for high power buck regulators on double-sided pcbs a single ground plane (usually the bottom) is recommended. 5) even though double sided pcbs are usually sufficient for a good layout, four-layer pcbs are the optimum approach to reducing susceptibility to noise. use the two internal layers as the power and gnd planes, the top layer for the high current connections and component vias, and the bottom layer for the noise sensitive traces. 6) keep the inductor switching node small by placing the output inductor, switching and synchronous fets close together. 7) the mosfet gate traces to the ic must be as short, straight, and wide as possible. ideally, the ic has to be placed right next to the mosfets. 8) use fewer, but larger output capacitors, keep the capaci- tors clustered, and use multiple layer traces with heavy copper to keep the parasitic resistance low. 9) place the switching mosfet as close to the +5v input capacitors as possible. 10) place the output capacitors as close to the load as possible. 11) place the v ffb ,v out filter resistors (510 ? ) in series with the v ffb and v out pins as close as possible to the pins. 12) place the c off and comp capacitors as close as possi- ble to the c off and comp pins. 13) place the current limit filter capacitors between the v ffb and v out pins, as close as possible to the pins. 14) connect the filter components of the following pins: v fb , v ffb , v out , c off , and comp to the lgnd pin with a single trace, and connect this local lgnd trace to the output capacitor gnd. 15) the ?roop?resistor (embedded pcb trace) has to be wide enough to carry the full load current. 16) place the v cc bypass capacitors as close as possible to the v cc pins and connect them to pgnd. layout guidelines
cs5132h 19 part number description cs5132hgdw24 24l so wide CS5132HGDWR24 24l so wide (tape & reel) d lead count metric english max min max min 24l so wide 15.60 15.20 .614 .598 thermal data 24l so wide r jc typ 16 c/w r ja typ 80 c/w package specification package dimensions in mm (inches) package thermal data ordering information on semiconductor and the on logo are trademarks of semiconductor components industries, llc (scillc). on semiconductor reserves the right to make changes without further notice to any products herein. for additional infor- mation and the latest available information, please contact your local on semiconductor representative. ?semiconductor components industries, llc, 2000 archive device not recommended for new design surface mount wide body (dw); 300 mil wide 1.27 (.050) bsc 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) d 0.32 (.013) 0.23 (.009) 1.27 (.050) 0.40 (.016) ref: jedec ms-013 2.49 (.098) 2.24 (.088) 0.51 (.020) 0.33 (.013) 2.65 (.104) 2.35 (.093) 0.30 (.012) 0.10 (.004)
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